PUSHW0=0, ENWRBUF=0, ENCACHE=0, PUSHW1=0, INVW0=0, INVW1=0, GO=0
Cache control register
| ENCACHE | Cache enable 0 (0): Cache disabled 1 (1): Cache enabled |
| ENWRBUF | Enable Write Buffer 0 (0): Write buffer disabled 1 (1): Write buffer enabled |
| RESERVED | no description available |
| INVW0 | Invalidate Way 0 0 (0): No operation 1 (1): When setting the GO bit, invalidate all lines in way 0. |
| PUSHW0 | Push Way 0 0 (0): No operation 1 (1): When setting the GO bit, push all modified lines in way 0 |
| INVW1 | Invalidate Way 1 0 (0): No operation 1 (1): When setting the GO bit, invalidate all lines in way 1 |
| PUSHW1 | Push Way 1 0 (0): No operation 1 (1): When setting the GO bit, push all modified lines in way 1 |
| RESERVED | no description available |
| GO | Initiate Cache Command 0 (0): Write: no effect. Read: no cache command active. 1 (1): Write: initiate command indicated by bits 27-24. Read: cache command active. |